Advantech MIC-5332 Uživatelský manuál

User Manual MIC-5332 AdvancedTCA® 10GbE Dual Socket CPU Blade with Intel® Xeon® E5-2600 series EP Processors

Chapter 1 Product Overview This chapter briefly describes the MIC-5332.

6.4.2 Activate HPM FPGA image Although the new FPGA is successfully downloaded to the board (called “deferred” version), it needs to be activated be

6.4.4 Verify successful Upgrade To verify the update process the hpm check of the IPMItool can be used again. Now the FPGA Backup Version should be

6.5.1 Upload new BIOS image Type IPMItool HPM.1 upgrade command and select the new BIOS image. 6.5.2 Activate HPM BIOS image Although the new FPGA

6.5.3 Payload Reset In order to activate the new BIOS image a payload reset is required. The payload reset can be performed through different ways

 6.6 NVRAM Upgrade In contrast to the BIOS image update, the setting update image is not directly written to any of the BIOS SPI flashes. The BIO

 [root@localhost ~]# ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x01 <section>

6.6.2 Upload new NVRAM image Type IPMItool HPM.1 upgrade command and select the new NVRAM image.  6.6.3 Activate HPM NVRAM image Since there exist

6.6.4 Payload Reset In order to activate the new NVRAM image a payload reset is required. The payload reset can be performed through different ways.

Appendix A IPMI/PICMG Command Subset Supported by IPMC

IPM Device “Global” Commands Command IPMI Spec RefNetFn CMDIPMI / PICMG3.0 / AMC2.0 Requirement Get Device ID 20.1 App 01h Mandatory Cold Reset

1.1 MIC-5332 Overview The MIC-5332 is a dual socket AdvancedTCA blade based on the Intel® Xeon E5-2600 series EP processors and C600 PCH (codename Pat

Set User Access 22.26 App 43h Optional Get User Access 22.27 App 44h Optional Set User Name 22.28 App 45h Optional Get User Name 22.29 A

Get Sensor Reading 35.14 S/E 2Dh Mandatory Get Sensor Type 35.16 S/E 2Fh Optional FRU Device Commands Command IPMI Spec RefNetFn CMDIPMI / P

AdvancedTCA® Commands Command PICMG® 3.0 TableNetFn CMDIPMI / PICMG3.0 / AMC2.0 Requirement Get PICMG Properties 3-11 PICMG 00h Mandatory Get Add

Advantech OEM commands Advantech management solutions support extended OEM IPMI command sets, based on the IPMI defined OEM/Group Network Function (Ne

A.2.1 LAN controller interface selection The MMC firmware provides an OEM IPMI command to allow users to switch the MMC connected NC-SI interface be

4 = Channel 2 is the only allowed port, always use it, never change to channel 1. The NC-SI LAN controller channel setting will be stored permanently

0x02 Front Panel RJ45 0x03 Front panel mini-USB (default)0x04 RTM mini-USB 0x05 RTM RJ45 0x0F Automatic mode Table 2: COM1 UART MUX settings COM2 M

A.3 Read Port 80 (BIOS POST Code) OEM command To be able to read out the actual BIOS boot state via IPMI, the MMC provides an Advantech OEM command t

6 PCH MAC 7 IPMC MAC 8..x FMM MAC addresses (if plugged) Table 4: MAC Address mapping table Read MAC Address OEM command: Response: A.6 Load D

Appendix B Zone 1 P10 Pin-out Pin pin name Pin use 1 Reserved No connected 2 Reserved No connected 3 Reserved No connected 4 Reserved No co

Mirroring.(please refer to chapter 4) Advantech IPMI firmware has been tested for CP-TA compliance using the Polaris Networks ATCA Test Suite. The MI

33 -48V_A -48V input feed A 34 -48V_B -48V input feed B

Appendix C Zone 2 Interface pin-out Zone 2 J20 pin out – Update Channel J20 Pin Row A B C D E F G H 1 N.C. N.C. N.C. N.C. N.C. N.C. N.

Zone 2 J22 pin out – Base Interface and Fabric Interface J22 Pin Row A B C D E F G H 1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.2 N.C.

Zone 2 J23 pin out – Base Interface and Fabric Interface J23 PinRow A B C D E F G H1 FI_CH2Tx2+FI_CH2Tx2‐FI_CH2Rx2+FI_CH2Rx2‐FI_CH2Tx3+

Appendix D Zone 3 Interface (RTM) pin-out Zone 3 J31 pin out J31 Pin Row M A 8 RTM_+12V RTM_3.3V_MP RTM_IPMBL 7 RTM_MMC_ RTM_PERST0# RTM_ENABLE

Zone 3 J32 pin out J32 Pin Row M A 8 notconnected notconnected RTM_USB3 RTM_USB27 TCLKD TCLKC TCLKB TCLKA6 notconnected notconnected5

3 PEx16_1:RTM_PE16‐1_10RXPEx16_1:RTM_PE16‐1_14RXPEx16_1:RTM_PE16‐1_10TXPEx16_1:RTM_PE16‐1_14TX2 PEx16_1:RTM_PE16‐1_3RXPEx16_1:RTM_PE16‐

Appendix E FMM Interface pin-out F E D C B A 1 NC GND FM_PRSNT# GND NC GND 2 GND NC GND FI3_RX0_P GND PCIE1_TX0_P 3 GND NC GND FI3_RX0

33 FPGA_GPIO_N7 GND PCIE0_RX7_N GND PCIE1_RX7_N GND 34 GND NC GND PCIE0_REF_CLK_P GND PCIE1_REF_CLK_P 35 GND NC GND PCIE0_REF_CLK_P GND PCIE1_REF_

27 GND FPGA_GPIO_N0 GND PCIE0_TX4_N 28 FPGA_GPIO_P2 GND PCIE0_TX5_P GND 29 FPGA_GPIO_N2 GND PCIE0_TX5_N GND 30 GND FPGA_GPIO_P4 GND PCIE0_TX6_P 31 GND

1.2 Block Diagram The hardware implementation is shown in the following block diagram. Refer to Table 1.1 (next page) for the detailed product technic

1.3 Product Configurations Model Name Configurations MIC-5332SA1-P1E MIC-5332 RJ45 version with dual Intel® Xeon® E5-2648L CPU MIC-5332SA1-P2E MIC

Chapter 2 Board Features This chapter describes the MIC-5332 hardware features.

2.1 Technical Data Processor System CPU Dual Intel® Xeon® E5-2648L/E5-2658 8-core processors(1) Max. Speed 2.1GHz Chipset Intel® C604 BIOS Dual 64-M

Environment Operating Non-operating Temperature 0 ~ 55° C (32 ~ 131° F) - 40 ~ 70° C (-40 ~ 158° F) Humidity 5 to 93%@40°C (non condensing) 95%

The E5 series Xeon processors support cache memory as listed below:  A 32-KB instruction and 32-KB data first-level cache (L1) for each core.  A

 PCIe hot swap is not supported for graphic controllers (e.g. FMM-5002E) installed on a RTM. 2.2.5 Redundant BIOS Flash The MIC-5332 has two SPI fl

Revision History Revision Index Brief Description of Changes Date of Issue 0.1 Initial Draft November 15th, 2011 0.2 Modification April 11th, 2012

Table 2.4 SATA Port Configuration on the MIC-5332 The MIC-5332 is also able to support SAS devices. 4 SAS 2.0 channels are reserved for SAS or SATA d

MIC-5332 are listed as table 2.7. Figure 2.2 DIMM slots on the MIC-5332 DIMM Type RDIMMs UDIMMs LRDIMMs Size 2GB, 4GB, 8GB, 16GB and 32GB 2GB, 4G

 Mirrored Channel Mode In Mirrored Channel Mode, the memory contents are mirrored between Channel 0 and Channel 2 and also between Channel 1 and Cha

The MIC-5332 also supports PXE boot and SoL (Serial-over-LAN) over the Base Interface channels. PXE boot can be enabled “Launch PXE OpROM” through th

I/O Interface Front Panel Intel® i350-AM4Ports 2, 3 Copper or Fiber 10/100/1000 Mb/s 9 Intel® 82579 Copper10/100/1000 Mb/s Table 2.8: Ethernet Inter

The FMM board is generally used to provide an option to expand the feature sets, both for the main board and RTM board. It is managed by the main boar

Chapter 3 Installation This chapter describes the procedure to install the MIC-5332 into a chassis. Peripherals (DIMMs, SSD) installation, jumper set

3.1 Processor The MIC-5332 is shipped with two CPUs and heat sinks installed. Please do not attempt to remove the heat sinks, or the cooling performan

1. Open the ejector on the empty DIMM socket where you want to install the DIMM. 2. Insert the memory module into the empty slot. Please align the n

connected and the user enters any character, the multiplexer will then switch the output to this interface as this is the latest request. The previous

Copyright The documentation and the software included with this product are copyrighted 2012 by Advantech Co., Ltd. All rights are reserved. Advantech

UART MUX Zone3 UART1 UART2 SoL miniUSB RJ45 Step2. When the user plugs another console cable into the MIC-5332, (e.g. miniUSB), the UART MUX w

Figure 3.2 UART Multiplexer Switching Mechanism RJ45 (COM1) For a terminal PC to connect to the console function on the MIC-5322 with a RJ45 to

convert data traffic between USB and UART formats. This chip includes a complete USB 2.0 full-speed function controller, bridge control logic, and a U

3.3.3 PuTTY Configuration Assuming both the CP2102 driver and PuTTY have been installed successfully on the terminal PC with Microsoft Windows, the u

Figure 3.3b PuTTY Configurations If the connection is successful and the user enters BIOS setup menu, upon boot the MIC-5332 BIOS setup menu will b

3.4 Installing the MIC-5332 3.4.1 MIC-5332 To install MIC-5332 into the chassis: 1. Leave the ejector handles in the open position. 2. Choose a node

Note:  Regarding the slot information, please refer to the backplane/chassis manual  The MIC-5332 also supports hot-swap, i.e. no need to turn of

FMM installed. Mounting instructions are still provided here to support customer development as well as inhouse RMA and repair. For installation of th

Figure 3.8 MIC-5332 w/ FMM module and SSD Bracket locations Figure 3.9 Locate the FMM site on the blade SSD Bracket FMM Module

Figure 3.10 Install the screws 3.4.3 RTM (Optional) For installation of the RTM, please refer to the RTM user manual. Please make sure that the RTM

Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring. W

For details, please contact your Advantech representative to obtain further support. Figure 3.9 MIC-5332 Front Panel Configuration 3.4.6 LED Defini

Display Status Bright … Blink Off Table 3.2 LED Signal Identification LED Name Function Display FI port 1/2/3/4 Speed/Link/ Active 10Gb/s

Note: FI channel 3 and 4 support is optional and only active when populating with the FMM-5001BE on the FMM site of the MIC-5332. 3.4.7 Jumper Settin

Figure 3.10 Jumper Locations JP1 JP5 JP6

Chapter 4 Hardware Management This chapter describes the IPMC firmware features.

4.1 Overview A complete management mechanism is strength of AdvancedTCA. An on board IPMC (Intelligent Platform Management Controller) is in charge of

Figure 4.1 IPMC Interface Block Diagram 4.2.1.1 IPMB-0 Interface The IPMB0 interface is the communication path between the ShMC and IPMC through Zone

Note: The IPMC firmware provides an OEM IPMI command to allow users to switch the IMPC/FPGA connected NC-SI interface between the front panel LAN IO a

LAN channel selection priority setting list: 0 = The first channel that links up, gets the NC-SI connection to the BMC. 1 = Channel 1 is the preferred

Field description Board information Format version 0x01 Board area length (calculated) Language code 0x19(English) Manufacturer date/time (Based

Warnings, Cautions and Notes Warning! Warnings indicate conditions, which if not observed, can cause personal injury. Caution! Cautions are includ

Assert Tag type/length 0xC0 Assert Tag (unused) FRU File ID type/length 0xCC FRU File ID frudata.xml Custom product info area fields (unused) C

Sensor Name Description FRU Device Locator IPMI FRU Device Locator HOTSWAP PICMG Frontboard Hotswap sensor HS_RTM PICMG RTM Hotswap sensor BMC_W

CPU1_CORE-VOL Threshold sensor CPU-1 Core Voltage CPU1_1_80-VOL Threshold sensor CPU-1 1.80V DDR_AB-VOL Threshold sensor DDR Voltage 1.5V DDR_CD-VO

Sensor Name Nominal Value LNR LCR LNC UNC UCR UNR V48-CUR range - - - 7.6 8.5 9.5 HU-CAP-VOL 65 0 - - 78 83 88 V48_A-VOL 48.0 36

area and the other one is located in the air outlet area. Temperatures of the DIMM air inlet and CPU are monitored by the CPU internal digital sensor,

4.3.3 Discrete sensors 4.3.3.1 IPMC Device Locator Each IPMC provides a PICMG compliant FRU device locator for the subsystem. This record is used to

4.3.3.8 VR HOT Sensor The IPMC contains a sensor to monitor the state of the voltage regulators on each subsystem. The sensor is implemented as a disc

BIOS Update Successful 0x03 0x00 Update Timeout 0x03 0x04 Update Aborted 0x03 0x02 Flash 0 boot Failed 0x03 0x29 Flash 1 boot Failed

If the BMC watchdog is enabled again for OS load supervision, the user needs to make sure the running OS will reset or disable the BMC watchdog afterw

console communication with the payload over a LAN interface (See Section 4.2.1.4, NC-SI Interface). The SoL function is available for I/O LAN (LAN1 &a

Safety Instructions 1. Read these safety instructions carefully. 2. Keep this User Manual for later reference. 3. Keep this equipment away from hum

3. Choose a proper connection (LAN, KCS, or IPMB) to the MIC-5332. Taking LAN for example, connect theFront Panel IO GbE-LAN RJ-45 port (LAN1 or LAN2

4.6.3 SoL Establishment 4.6.3.1 Serial over LAN Serial over LAN (SOL) is an extension to IPMI over LAN (IOL) and allows to transmit serial data vi

<1.1> Supported LAN interfaces Four of MIC-5332’s Ethernet interfaces can be used for Serial over LAN: ‐ Base interface channel 1/2 ‐ I/O in

To get an overview of all possible commands within an IPMItool command group, please use the single keywords (e.g. “lan”, “user” or “sol”) only. <

<2.2> User Commands - user list Get the list of all supported users. - user set name <user id> [username] This command can be used to c

Command Line Syntax: -I lan Specifies Ethernet interface -H <IP-Address> IP address assigned to the IPMC -U <User> User account, def

<3.2> SOL session activation Finally, the IPMItool “sol activate” command need to be issued to establish the SOL session to MIC-5332 from rem

replying the predefined value, e.g. 300W to the shelf manager, the MIC-5332 IPMC uses an intelligent mechanism to auto-detect current CPU type and the

4.9 RTC Synchronization In every ATCA system there are several different clock sources. To avoid differences in the time values, a synchronization m

Figure 4.4 Real Time Clock Synchronization Overview From IPMC’s point of view are two more participants in an ATCA System, which maintain their own

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Chapter 5 AMI APTIO BIOS Setup This chapter describes how to configure the AMI APTIO BIOS (UEFI BIOS).

5.1 Introduction The AMI BIOS has been customized and integrated into many industrial and embedded motherboards for over a decade. In order to extend

showing basic BIOS and blade information.Press <DEL> or <F2> and users will immediately be allowed to enter Setup. Figure 5.2 Press <

IPMC Version Display only Show IPMC version FPGA Version Display only Show FPGA version SPI Active Display only Show the active SPI Time Zone GMT

Figure 5.3 Advanced BIOS Features Setup Snapshot Feature Default Description Launch PXE OpROM DisabledEnable or Disable Boot Option for Legacy Ne

5.4.1 PCI Subsystem Settings Figure 5.4 PCI Subsystem Settings Table 5.3 PCI Subsystem Settings 5.4.1.1 PCI Express Settings Users can enter in th

5.4.2 ACPI Settings Figure 5.5 ACPI Settings Table 5.4 ACPI Settings 5.4.3 Trusted Computing Feature Default Description Enable ACPI Auto Conf

Figure 5.6 Trusted Computing Table 5.5 Trusted Computing 5.4.4 WHEA Configuration The user can enable or disable the Windows Hardware Error Archite

Figure 5.7 WHEA Configuration 5.4.5 CPU Configuration Figure 5.8 CPU Configuration Feature Default Description Socket 0 CPU Information Displa

Table 5.6 CPU Configuration 5.4.5.1 CPU Power Management Configuration Users can enter into the submenu to configure CPU power management. The eser c

Glossary ACPI Advanced Configuration and Power Interface AHCI Advanced Host Controller Interface AMC Advanced Mezzanine Card APIC Advanc

User can enable or disable the runtime error logging support via a sub option of the advanced setting (default is disabled). Figure 5.9 Runtime Err

Table 5.7 SATA Configuration The MIC-5332 supports total 6 SATA devices (details, please refer to section 2.2.6). Users can check the status each by

The MIC-5332 supports USB Plug & Play, PnP. That is, users can find all USB devices which are plugged on the MIC-5332. They can configure the para

5.4.10 UART MUX Configuration The MIC-5332 supports two UART channels. Users can select the different methods (SoL, FP-RJ45, FP-USB, RTM0 and RTM1) t

Table 5.9 Serial Port Console Redirection Figure 5.14 Serial Port Console Redirection 5.4.12 Network Stack Users can enable or disable the network

Figure 5.15 Network Stack 5.4.13 iSCSI This function allows users to give a worldwide unique name for the iSCSI initiator. Figure 5.16 iSCSI Initia

Also, users can find the corresponding MAC address for each LAN here. Figure 5.17 Main Configuration Page 5.5 Chipset Setup Select the chipset tab fr

Figure 5.16 Chipset Configuration 5.5.1 North Bridge Users can set up all parameters related to the IOH function in the North Bridge page. Moreover,

Figure 5.17 North Bridge Configuration 5.5.2 South Bridge Users can set up all parameters related to the PCH function in the South Bridge page. Also

Table 5.11 South Bridge Configuration Figure 5.18 South Bridge Configuration Disable SCU devices Disabled Enable/Disable Patsburg SCU Devices.

ShMC Shelf Manager Controller SOL Serial Over LAN TCLK Telecom Clock TPM Trusted Platform Module TX Transmit UDIMM Unbuffered DIMMs U

5.6 Server Management (Mgmt) Setup Users can configure the watchdog timer both for the FRB-2 and OS Wtd in the server mgmt page. For details of the BM

Table 5.12 Server Mgmt Configuration 5.7 Boot Setup Users can configure the system boot priority settings via the boot page. The default setting of b

Table 5.13 Boot Configuration 5.8 Security Setup The two items “Administrator Password” and “User Password” allow users to configure the system so th

 If ONLY the Administrator's password is set, then this only limits access to Setup and is only asked for when entering Setup.  If ONLY the U

Table 5.14 Save & Exit Configuration Restore Defaults Restore/Load Default values for all the setup options. Sa

Chapter 6 Firmware Upgrade This chapter describes how to update the IPMC FW, FPGA and BIOS for the MIC-5332.

6.1 HPM.1 Upgrade Functionality All firmware updates/upgrades (IPMC firmware, FPGA configuration and BIOS SPI Flash) can be performed through HPM.1 ov

[root@localhost ~]#ipmitool hpm upgrade mic5332_standard_hpm_fw_00_46.img PICMG HPM.1 Upgrade Agent 1.0.2: Validating firmware image integrity.

6.3.2 Activate HPM FW image Although the new IPMC FW is successfully downloaded to the board (called “deferred” version), it needs to be activated be

[root@localhost ~]#ipmitool hpm upgrade mic5332_standard_hpm_fpga_02_14.img PICMG HPM.1 Upgrade Agent 1.0.2: Validating firmware image integrity.