Advantech PCI-1720 Uživatelský manuál stáhnout pdf (Strana 40)

36 PCI-1713 User's Manual

A.1 Introduction

The PCI-1713 uses one Intel 82C54 compatible programmable

interval timer/counter chip. This popular 82C54 offers three indepen-

dent 16-bit counters, counter 0, counter 1 and counter 2. Counter 0 is

not available for users. Counter 1 is cascaded with counter 2 to create

a 32-bit timer for the pacer trigger. A low-to-high edge of counter 2

output can trigger an A/D conversion, and users can utilize this signal

as a synchronous signal for other applications.

A.2 Counter Read/Write and Control

Registers

The 82C54 programmable interval timer uses four registers at address-

es BASE + 24(Dec), BASE + 26(Dec), BASE + 28(Dec) and

BASE + 30(Dec) for read, write and control of counter functions.

BASE + 24(Dec) Counter 0 read/write

BASE + 26(Dec) Counter 1 read/write

BASE + 28(Dec) Counter 2 read/write

BASE + 30(Dec)Counter control word

Since the 82C54 counter uses a 16-bit structure, each section of

read/write data is split into a least significant byte (LSB) and most

significant byte (MSB). To avoid errors it is important that you make

read/write operations in pairs and keep track of the byte order.

The data format for the control register appears below:

BASE+30(Dec) 82C54 control, standard mode

Bit D7 D6 D5 D4 D3 D2 D1 D0

Value SC1 SC0 RW1 RW0 M2 M1 M0 BCD

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 53 54

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Advantech PCI-1720 Uživatelský manuál Strana 40