Advantech PCA-6180 Specifikace stáhnout pdf (Strana 58)

40 PCA-6180 User’ s Manual

Figure 3-5: Advanced chipset features screen

3.5.1 SDRAM CAS Latency Time

This controls the latency between SDRAM read command and the

time that the data actually becomes available. Leave this on the

default setting.

3.5.2 SDRAM Cycle Time Tras/Trc

This selects the number of SCLKs for an access cycle.

3.5.3 SDRAM RAS-to-CAS Delay

This controls the latency between SDRAM active command and the

read/write command. Leave this on the default setting.

3.5.4 SDRAM RAS Precharge Time

This controls the idle clocks after issuing a precharge command to

SDRAM. Leave this on the default setting.

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Advantech PCA-6180 Specifikace Strana 58